[Lab] Verilog Help

[Paul & Andrea Mumby]

Hey, anyone on the list good with Verilog?

I'm working on an FPGA project, and my Verilog is VERY rusty lol (last used
it ages ago, and even then only for simple logic projects, not a full FPGA
solution)

I'm having some trouble with simulating some of my code, and was hoping for
some pointers on optimizing my design somewhat. Any help would be
appreciated.

The issue I'm having is related to pipelining...

I have a generate block, containing a for loop

so for example:

generate
for(i=0; i<10; i=i+1) begin: STAGE
reg invalue;
reg outvalue;
MyModule MOD (
.input(invalue)
.output(outvalue)
);
always @ (posedge clk) begin
if(i>0) begin
invalue <= STAGE[i-1].outvalue;
end
end
end
endgenerate

This is of course just an example, but it gets the idea across.
(specifically I'm trying to build an optimized pipelined SHA256 Crypto
Processor)

The code synthesizes fine, but the simulator throws an error on the
line invalue <= STAGE[i-1].outvalue;
saying <STAGE[-1].outvalue> is not declared.

It's like it's ignoring the if statement.

This is using Xilinx ISE specifically (I'm targeting a Spartan6)

I can provide specific code if it would help, but it's not an opensource
project so I'd need "assurances" that it won't get distributed :) (it will
be opensourced eventually but not right away)

Beyond that, as I said my verilog is rusty as hell, so any pointers on
optimizing would be appreciated too. Right now my main constraint seems to
be routing delay (I'm sitting at 12ns right now, I'd ideally like to get
that much lower, closer to 5ns)

Thanks!

- Paul
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