Hey, anyone on the list good with Verilog?<div><br></div><div>I'm working on an FPGA project, and my Verilog is VERY rusty lol (last used it ages ago, and even then only for simple logic projects, not a full FPGA solution)</div>
<div><br></div><div>I'm having some trouble with simulating some of my code, and was hoping for some pointers on optimizing my design somewhat. Any help would be appreciated.</div><div><br></div><div>The issue I'm having is related to pipelining... </div>
<div><br></div><div>I have a generate block, containing a for loop</div><div><br></div><div>so for example:</div><div><br></div><div>generate</div><div>for(i=0; i<10; i=i+1) begin: STAGE</div><div>reg invalue;</div><div>
reg outvalue;</div><div>MyModule MOD (</div><div>.input(invalue)</div><div>.output(outvalue)</div><div>);</div><div>always @ (posedge clk) begin</div><div>if(i>0) begin</div><div>invalue <= STAGE[i-1].outvalue;</div>
<div>end</div><div>end</div><div>end</div><div>endgenerate</div><div><br></div><div>This is of course just an example, but it gets the idea across. (specifically I'm trying to build an optimized pipelined SHA256 Crypto Processor)</div>
<div><br></div><div>The code synthesizes fine, but the simulator throws an error on the line invalue <= STAGE[i-1].outvalue;</div><div>saying <STAGE[-1].outvalue> is not declared.</div><div><br></div><div>It's like it's ignoring the if statement.</div>
<div><br></div><div>This is using Xilinx ISE specifically (I'm targeting a Spartan6)</div><div><br></div><div>I can provide specific code if it would help, but it's not an opensource project so I'd need "assurances" that it won't get distributed :) (it will be opensourced eventually but not right away)</div>
<div><br></div><div>Beyond that, as I said my verilog is rusty as hell, so any pointers on optimizing would be appreciated too. Right now my main constraint seems to be routing delay (I'm sitting at 12ns right now, I'd ideally like to get that much lower, closer to 5ns)</div>
<div><br></div><div>Thanks!</div><div><br></div><div>- Paul</div>